Cyclic redundancy check (CRC) is commonly performed on data, to determine whether errors have been incorporated into the data. Prior to transmission, payload data is processed through a polynomial, and a resulting word (an error detection code EDC) is generated and is appended to the data. At a receiving end, the payload data is processed through the same polynomial in a CRC circuit. If the same EDC results, the received data is considered to be valid. Errors in the data will of course result in a different EDC, and the receiving equipment will then typically signal the data transmitter to repeat the data sequence.
Originally, data was applied to a CRC circuit in a bit-serial fashion. However, in order to obtain a high throughput, such as is required in asynchronous transfer mode (ATM) circuits, the payload data must be input to the CRC circuit in a bit parallel fashion. The bit parallel data input presents a problem for CRC implementations. For example, in the system described in the publication "High Speed Parallel CRC Circuits in VLSI", by T. Pei and C Zukolowsi, IEEE Transactions on Communications, pp. 653-657, Vol. 40, No. 4, April, 1992, the signal translation algorithms require that the input data wordlength should be smaller than the CRC generator polynomial wordlength. Thus, in the case of ATM cells, the input data word must be 10 bits or less. This imposes a throughput restriction.
In addition, a reserved field in the 47th byte of the payload of the ATM AIS cell can present a problem for parallel CRC-10 (CRC polynomial having a 10 bit detection code) generators. If the input wordlength is not equal to the reserved field wordlength, an additional cycle is required to compute the CRC of the cell, since such CRC computations assume a fixed input wordlength. Thus, in this case the input wordlength would have to be 6 bits, (to accommodate 10 bits, two parallel 6 bit CRC calculations must be used) which can reduce the overall throughput of the device.